FIG. 1 illustrates a microprocessor 10 coupled to a memory device 12 via data bus 14. Data bus 14 includes a plurality of conductive lines (not shown) for transmitting data bit signals and a strobe signal in parallel between memory device 12 and microprocessor 10. As used herein, a memory device may include SRAMs, DRAMs, or other memory capable of storing digital data.
Microprocessor 10 includes a plurality of input/output (“I/O”) devices (not shown in FIG. 1) coupled to respective conductive lines of data bus 14. These I/O devices are capable of transmitting or receiving data bit signals. FIG. 2 shows relevant components of I/O devices of microprocessor 10. More particularly, FIG. 2 shows a plurality of FIFOs 20(0) through 20(n) each one of which is contained in a respective I/O device. FIG. 2 also shows a strobe buffer 22. Lastly, FIG. 2 shows a plurality of data buffers 24(0) through 24(n) each one of which is contained in a respective I/O device.
Data buffers 24(0) through 24(n) are coupled between respective data inputs of FIFOs 20(0) through 20(n) and respective conductive lines of data bus 14. The output of strobe buffer 22 is coupled between a conductive line of data bus 14 and FIFOs 20(0) through 20(n). For purposes of definition, two devices (e.g., a buffer and a FIFO) may be coupled together directly by a conductor or data link, or indirectly via a third device. For example, FIG. 2 show data buffers 24(0) through 24(n) coupled directly to data inputs of FIFOs 20(0) through 20(n), respectively. Further, although not shown, buffers 24(0) through 24(n) are coupled indirectly to respective data bus lines via output bumps of microprocessor 10 and conductive traces of a semiconductor packaging in which microprocessor is contained.
Data bus 14 transmits the strobe signal in parallel with data bit signals. The strobe signal is essentially a clock having a 50% duty cycle. Memory 12 transmits data at a double data rate (DDR). More particularly, I/O devices of memory 12 transmit a set of data bit signals Din(0) through Din(n) with each transition edge (i.e., a rising edge and falling edge) of the strobe signal.
Data bit signals Din(0) through Din(n) are received by data buffers 24(0) through 24(n) around the same time strobe buffer 22 receives the transition edges of the strobe signal. Buffers 22 and 24(0) through 24(n), when the enable signal provided thereto are asserted, transmit the strobe signal and data bit signals Din(0) through Din(n) to FIFOs 20(0) through 20(n).
FIFOs 20(0) through 20(n) capture or store data bit signals Din(0) through Din(n), respectively, upon the transition edges of the strobe signal provided thereto by strobe buffer 22. FIFOs 20(0) through 20(n) store data bit signals Din(0) through Din(n), respectively, for subsequent processing by the core of microprocessor 10. It is essential that that FIFOs 20(0) through 20(n) receive the transition edges of the strobe signal during a read data capture timing window. The read data capture timing window is a period of time when: (1) all data bit signals Din(0) through Din(n) are present at the inputs of FIFOs 20(0) through 20(n) with sufficient set-up time before FIFOs 20(0) through 20(n) receive transition edges of the strobe signal from buffer 22, and; (2) all data bit signals Din(0) through Din(n) are present at the inputs of FIFOs 20(0) through 20(n) with sufficient hold time after FIFOs 20(0) through 20(n) receive the transition edges of the strobe signal from buffer 22. If the transition edges of the strobe signal do not arrive at FIFOs 20(0) through 20(n) during the read capture timing window, false data will be stored in FIFOs 20(0) through 20(n).
Transmission of the strobe signal and data bit signals Din(0) through Din(n) between memory device 12 and FIFOs 20(0) through 20(n), are subject to unexpected delays. Because of relative delays in the transmission of the data bit signals Din(0) through Din(n) to the inputs of FIFOs 20(0) through 20(n), the read capture timing window may be substantially small. Additionally, because of unexpected delays, the transition edges of the strobe signal may arrive at FIFOs 20(0) through 20(n) with an unexpected delay relative to the read capture timing window.
A variety of factors induce transmission delay in the data bit and strobe signals. For example, the conductive line of bus 14 that transmits the strobe signal may be shorter or longer in length than one or more of the conductive lines of bus 14 that transmit the data bit signals. Another source of relative signal delay relates to variations in the process used to manufacture microprocessor 10. Microprocessors are manufactured using complex equipment and processes. Variations in the equipment and processes may result in unexpected physical variations of the structure of, for example, the transistors in strobe buffer 22. These physical variations in transistor structure may introduce unexpected delays in the strobe signal transmitted through strobe buffer 22.
The unexpected delays described above are fixed. Delays in the strobe and data bit signals may vary. For example, delays in the strobe signal may vary during operation of the microprocessor due to changes in temperature of strobe buffer 22 or changes in the power supply voltage provided to strobe buffer 22. Increases in operating temperature of strobe buffer 22 will typically increase delay in strobe signal transmission therethrough, and vice versa. An increase power supply voltage provided to strobe buffer 22 will typically decrease delay in strobe signal transmission therethrough, and vice versa.
As noted above, the transition edges of strobe signal and the data bit signals Din(0) through Din(n) are received by buffers of microprocessor 12 around the same point in time. FIG. 3 is a timing diagram illustrating the data bit signal Din(0) and the strobe signal provided to inputs of FIFO 20(0). Except for relative delays between data signals, inputs to the remaining FIFOs 20(1) through 20(n) are identical. Strobe buffer 22 is designed to delay transmission of the strobe signal by a fixed amount of time (e.g., 25% of the strobe signal's duty cycle) so that FIFOs 20(0) through 20(n) receive the transition edges (e.g., rising edge at time=t1) within a read capture timing window thereof.
FIG. 3 illustrates the relative effects of unexpected delays on the strobe signal. In FIG. 3, unexpected delays may cause the transition edges of the strobe signal to move in time relative to data bit signal Din(0) in either the Dpositive or Dnegative directions by an undetermined magnitude. Unfortunately, if the magnitude of Dpositive or Dnegative is great enough, the transition edges of the strobe signal may fall outside the read capture timing window.